1. Field of the Invention
The present invention relates to a structure of an active matrix display (including an active matrix type liquid crystal display device, an EL display device, and an EC display device) which is constituted by thin film transistors (TFTs) formed by using a crystalline thin film semiconductor. Also, the present invention relates to an electrooptical device using such an active matrix display as a display device.
2. Description of the Related Art
In recent years, there has been rapidly developed a technique in which a pixel matrix circuit and a driving circuit are integrally formed on the same substrate by using TFTs. The reason is that the demand for an active matrix display (also called an active matrix panel) has been increased in everyday life.
In the active matrix display, a TFT is disposed for each of a plurality of pixels arranged in matrix, and an electric charge going in and out of each of pixel electrodes (driving electrodes) is controlled by a switching function of the TFT.
As such an active matrix display, there is known one disclosed in U.S. Pat. No. 5,250,931 (Misawa et al.). The U.S. Patent discloses an active matrix panel in which a pixel matrix and driver circuits (source line driver circuit and gate line driver circuit) are formed on the same substrate, and also discloses applied products thereof. The U.S. patent discloses that the driver circuit is constituted by a shift register, a sample-and-hold circuit, a buffer and the like.
As disclosed in the above patent, the conventional active matrix display is only constituted by the pixel matrix and the driver circuit on the same substrate. However, in the present everyday life, the active matrix display is used for various applied products (electrooptical devices and the like), and there are increasing requests for miniaturization, improvement of performance, and decrease of consumption of electric power.
In such circumstances, an SOP (System On Panel) plan has been recently proposed as means for miniaturizing the active matrix display and improving the performance thereof. The SOP plan is a plan to mount a logic circuit (signal processing circuit such as a display control circuit and an arithmetic circuit), which is conventionally externally equipped to the active matrix display, on the same substrate by using TFTs.
However, a technique for forming TFTs capable of realizing the plan has not been established. The reason is that it is difficult to constitute an electric circuit requiring high frequency driving, such as a logic circuit, by TFTs using presently employed silicon thin films.
For example, in the current circumstances, there are well known a TFT using a silicon thin film (so-called high temperature polysilicon) formed through a heat treatment at about 900.degree. C., and a TFT using a silicon thin film (so-called low temperature polysilicon) formed at a relatively low temperature of 600.degree. C. or less. However, it is difficult to realize a TFT having such high speed performance that the TFT can constitute a logic circuit, by these silicon thin films.
Although the operating speed of a TFT can be tentatively improved by decreasing the size of the TFT, the reduction of a channel length (or gate length) causes a short channel effect, so that a trouble such as lowering of a drain withstand voltage occurs. Thus, in the case of a TFT using a conventional silicon thin film, the improvement of an operating speed by a scaling law reaches the limit, and it is difficult to further raise the operating speed in view of reliability. Also, there is a problem that crystal grains and crystal grain boundaries (grain boundaries) irregularly exist in the silicon thin film and the grain boundaries greatly affect the TFT characteristics to cause unevenness.
As described above, in the conventional TFT manufacturing technique, although the active matrix display as disclosed in the above U.S. patent can be constituted, it is difficult to integrate a logic circuit requiring higher speed operation.
In the case of a conventionally used IGFET (Insulated Gate Field Effect Transistor) formed on single crystal silicon, it is possible to form the IGFET which can operate at both low frequency driving and high frequency driving by using the extremely superior crystallinity of the single crystal. However, in the IGFET formed on a single crystal silicon wafer, there is a problem that if a channel length is shortened to raise an operating speed, a short channel effect immediately becomes tangible.
Accordingly, since the IGFET for high frequency driving requires a specific treatment such as channel doping, it is common to separate an IC chip for high frequency driving from an IC chip for low frequency driving (for high withstand voltage driving) in order to avoid complication of manufacturing steps.
Thus, in the conventional technique, it is difficult to mount both a logic circuit for high frequency driving and a logic circuit for low frequency driving on the same substrate or the same chip, which causes a serious difficulty in realizing the SOP plan.